TSMC chip unit plans: Taiwan's TSMC is exploring the possibility of setting up advanced packaging capacity in Japan, sources familiar with the matter told Reuters. The move could boost Japan's efforts to rejuvenate its semiconductor industry.

The discussions are in preliminary stages, with one option being to introduce TSMC's chip on wafer on substrate (CoWoS) packaging technology to Japan. 

CoWoS is a high-precision technology that involves stacking chips on top of each other, enhancing processing power while saving space and reducing power consumption.

While no decisions have been made regarding the scale or timeline of potential investment, TSMC aims to double CoWos output this year, with further increases planned for 2025.

Establishing advanced packaging capacity in Japan would complement TSMC's existing operations in the country, where it has recently constructed one plant and announced another, both located on the southern island of Kyushu. 

Additionally, TSMC has set up an advanced packaging research and development center in Ibaraki prefecture.

Japan's semiconductor industry is well-positioned to embrace advanced packaging, supported by leading materials and equipment manufacturers, growing investment in chip fabrication capacity, and a robust customer base.

While TSMC's plans in Japan have received support from the government, including generous subsidies, other major players like Intel and Samsung are also eyeing opportunities in the country's semiconductor sector. 

Intel is considering establishing an advanced packaging research facility, while Samsung is setting up a research facility in Yokohama and exploring collaborations with Japanese companies for material procurement.

(With Reuters Inputs)